The present invention generally relates to measures to be taken to increase the noise immunity of a semiconductor device. More particularly, this invention relates to a technique of enhancing the noise immunity of a semiconductor device including not only an STI (shallow trench isolation) structure and a silicide diffused layer but also a dummy diffused layer for use in eliminating dishing, for example.
In the past, a LOCOS isolation technique was often used to electrically isolate the active region of devices included in a semiconductor integrated circuit. Recently, however, an STI process is adopted more and more frequently to define even finer patterns. This tendency manifested itself when the design rule for LSIs reached 0.25 μm or 0.18 μm.
On the other hand, silicidation techniques have also been preferred lately. A silicidation technique is applicable to a process of forming a titanium or cobalt alloy layer, for example, on the upper surface of a diffused layer or a gate electrode. The silicidation was found effective because of several different reasons. Firstly, reduction in design rule for a semiconductor process has decreased the cross-sectional areas of diffused layer, gate electrode, contacts and so on. Accordingly, it is now much more necessary to reduce the parasitic resistance. Secondly, in forming a diode with a dual-gate structure, the gate electrodes of p- and n-channel transistors included in the diode should be “backed”. As used herein, “backing” means connecting a low-resistivity conductor in parallel to the electrode.
It will be described in further detail why the “backing” is necessary.
In processes for the devices in 5 to 3 V supply voltage generations, the p-channel transistor used to have a buried channel, the n-channel transistor a surface channel and the gate electrodes of these transistors used to be made of n-type polysilicon. However, a supply voltage for an LSI has been reduced at a tremendously high rate (e.g., at an interval of about two years) these days. Specifically, a supply voltage of 3.3 V, which was a commonplace around ten years ago, has been replaced with 2.5 V, 1.8 V, 1.5 V, and so on. Even though the supply voltage has been reduced this way, the drive current still should be kept high with the standby current minimized. To meet those needs, a dual-gate process is preferably performed so that the p-channel transistor, as well as the n-channel transistor, may also have a surface channel.
To realize a dual-gate structure, however, the gate electrode of the n-channel transistor should be of n-type, while that of the p-channel transistor should be of p-type. Accordingly, a pn junction diode is unintentionally formed at the junction between the p- and n-type gates. Where such a diode exists between these transistors, a signal potential cannot change its level fully, thus making it very difficult to design an LSI normally.
For that reason, a low-resistivity silicide interconnect is formed on the gate electrodes to “back” them. In that case, there is no need for the designer to provide any additional interconnection layer for the backing purposes during the layout stage. As a result, the efficiency of the design process improves. In addition, the silicidation also contributes to reducing a cell area and utilizing an interconnection layer much more efficiently. Accordingly, the majority of those skilled in the art now adopt the silicidation for a dual-gate process.
FIG. 15 illustrates a schematic flow of a semiconductor device fabrication process including the steps of forming an STI structure and performing a silicidation process. FIGS. 16A through 16G are cross-sectional views illustrating schematic structures, corresponding to respective process steps for fabricating a semiconductor device, according to the flow illustrated in FIG. 15.
First, in Step S11 of forming STI regions, parts of a silicon substrate 100, where STI regions 101 and 102 will be defined, are etched to a predetermined depth by using a mask for defining diffused regions to form openings as shown in FIG. 16B. Next, the openings are filled with a field oxide film 103 as a material for the STI regions 101 and 102 as shown in FIG. 16C. Then, excessive parts of the field oxide film 103, existing over the filled parts, are removed by a CMP (chemical/mechanical polishing) process, thereby planarizing the surface of the substrate as shown in FIG. 16D.
A CMP polish pad usually has some elasticity. Accordingly, if there is any STI region 102 with a large area, then the field oxide film 103 existing in the region 102 might be partially removed excessively around its center. As a result, that part of the field oxide film 103 might have its height decreased by a level difference d as shown in FIG. 16D. This unwanted phenomenon is called “dishing”, which is often observable in a CMP process. The level difference d created in this manner (which will be herein called a “dishing level difference”) will deform a pattern to be defined in a subsequent lithographic process because the depth of focus will be insufficient. In addition, the characteristics of the resultant transistor will also be affected eventually. To avoid these inconveniences, the dishing level difference d should be eliminated from the CMP process.
If a harder CMP polish pad is used, the dishing may be eliminated without modifying the flow of the fabrication process itself. However, it would be more effective to place a dummy diffused layer 105, in which no source/drain electrodes will be actually formed for the transistor, in the STI region 102 with a large area at the layout stage. If the dummy diffused layer 105 is formed through the process steps illustrated on the right-hand side of FIGS. 16B, 16C and 16D, then the polish pad will not be forced into the field oxide film 103 so strongly. As a result, the dishing level difference d can be substantially eliminated.
Thereafter, in Step S12, a polysilicon gate electrode 106 is formed on the substrate 101 as shown in FIG. 16E. Then, in Step S13, p- or n-type dopant ions 108 are implanted into the substrate 101 using a mask 107 to define source/drain regions as shown in FIG. 16F. Subsequently, in Step S14, the diffused regions and polysilicon gate electrode 106 are covered with a silicide layer 109 as shown in FIG. 16G. In this manner, all the process steps on the bulk portion of the wafer are finished. And then interconnects are formed in Step S15, thereby completing an LSI.
As described above, the dummy diffused layer is very effectively applicable to preventing the dishing phenomenon from occurring in forming the STI regions by a CMP process. The dummy diffused layer may also have beneficial effects on different types of processes (like lithographic and etching processes) other than the STI process. For example, to define a fine-line pattern for a diffused layer accurately by a lithographic process, the percentage of the area covered by the diffused layer to the area of a predetermined region may have to fall within a prescribed range in accordance with a process condition. In that situation, a dummy diffused layer may be have to be placed so that the area percentage of the diffused layer can fall within the prescribed range.
However, through experiments and modeling, the present inventor found that a dummy diffused layer like that might unintentionally encourage the propagation of noise among circuit blocks as the case may be.
Now, it will be described with reference to FIGS. 17A through 19B how I found the problem to be solved by the present invention.
Suppose an analog block 50 susceptible to noise and a digital block 51 operating at a high speed to generate a lot of noise should be formed on the same substrate as shown in FIG. 17A. In that case, the analog block 50 is spaced way apart from the digital block 51 to reduce the noise propagated from the digital block 51 through a p-type substrate 52 by increasing the resistance formed by the substrate 52 with a p-well 53. That is to say, an STI region 54 with a large area is defined between the analog and digital blocks 50 and 51.
In an LSI, a sheet resistance of the p-well 53 is normally on the orders of several hundreds to several thousands Ω/□. Accordingly, by spacing the analog and digital blocks 50 and 51 sufficiently apart from each other, the resistance formed by the p-type substrate 52 with the p-well 53 can be relatively high.
However, when the large-area STI region 54 is defined in a CMP process, the dishing might occur in the region 54 as described above. To avoid this unwanted phenomenon, a dummy diffused layer 55 may be inserted into the STI region 54 as shown in FIGS. 18A and 18B. Then, it is possible to prevent the dishing.
Nevertheless, when another diffused layer and gate electrode have their surfaces turned into silicide alloys, this dummy diffused layer 55 also has its surface silicided. Thus, the dummy diffused layer 55 will have a two-layer structure in which a silicide layer 55b is formed over the remaining, non-alloyed part 55a. As a result, a low-impedance noise propagation path NZb, passing through the silicide layer 55b over the non-alloyed dummy diffused layer 55a, is newly made between the analog and digital blocks 50 and 51.
FIGS. 19A and 19B are circuit diagrams illustrating two models of the inter-block noise propagation path that correspond to the structures shown in FIGS. 17B and 18B, respectively. As shown in FIG. 19A, the structure shown in FIG. 17B has only a noise propagation path NZa, passing through the p-type substrate 52 with the p-well 53, between the analog and digital blocks 50 and 51. And this noise propagation path NZa has a relatively high inter-block resistance R1.
In contrast, the structure shown in FIG. 18B has not only the noise propagation path NZa but also another noise propagation path NZb, passing through the silicide layer 55b over the dummy diffused layer 55a, between the analog and digital blocks 50 and 51 as shown in FIG. 19B. Also, the resistance R1 and another resistance R2, which is lower than the resistance R1, are connected in parallel between the analog and digital blocks 50 and 51. The silicide layer 55b has a sheet resistance of approximately several Ω/□, whereas the p-well 53 has a sheet resistance of approximately several hundreds to several thousands Ω/□. Accordingly, the impedance values associated with these members 55b and 53 are different from each other by as much as two to three orders of magnitude.
For that reason, even if the resistance R1 formed by the p-type substrate 52 with the p-well 53 is much increased by spacing the analog and digital blocks 50 and 51 far apart, the impedance between these blocks 50 and 51 decreases considerably. This is because the resistance R2, formed by the backed silicide layer 55b, is connected in parallel between these blocks 50 and 51.
Accordingly, noise, generated by a VSS power supply DVSS for the digital block 51, is propagated to the vicinity of the analog block 50 by way of the silicide layer 55b. Then, the noise passes through the p-type substrate 52 again to affect a VSS power supply AVSS for the analog block 50. As a result, the analog block 50, which is easily affected by noise, possibly operates erroneously or have its characteristics degraded.
The silicided dummy diffused layer does not encourage the noise propagation just in the structure shown in FIG. 18B, but may cause similar noise problems in semiconductor devices with various other structures. For example, noise might also be propagated in a similar manner between a pair of circuit blocks connected together by an n-well or even in a single block.